1. Field of the Invention
This invention relates to digital phase-locked loops in general and, more particularly, to digital phase-locked loops used in clock recovery of burst-mode data systems.
2. Description of the Prior Art
Digital communication systems typically operate as one of two types: continuous mode and burst-mode. The difference between continuous-mode and burst-mode is the continued presence of pulses, such as data or clock pulses, for the former and the presence of the pulses only when data is to be transmitted for the latter. With continuous pulses, synchronization between receiver and transmitter is relatively simple and straightforward, such as that used in digital channel banks for telephony applications. However, integrated services digital networks (ISDN) and local area networks (LAN) are mostly burst oriented, particularly where multiple users are on a common communication bus, such as coaxial cable "backbone". Since each transmitter transmits only when information is to be transferred, all receivers "listening" thereto must synchronize to the data burst and each burst will have a different phase and a slightly different frequency from the preceding burst. This makes each burst independent of any preceding burst, complicating the synchronization procedure and hardware for each receiver.
To receive data reliably, the incoming burst data signal is sampled and a decision is made based on that sample whether a "one" or "zero" was transmitted. The sampling must be done at the optimal time so that the received signal amplitude is at its maximum or minimum; i.e., the data signal is sampled when the opening of the eye diagram is the greatest. The sampling is in response to a sampled clock which is derived from the incoming data signal. Since the data signal is not present at all times in a burst-mode environment, in contrast with the continuous-mode communication system environment, the sample clock must have the correct phase and frequency before the arrival of the data. To do so, the transmitter sends a "preamble" to the data, the preamble consisting of a predetermined length of alternating "one"s and "zero"s, creating a clock signal which can be utilized to generate the proper sample clock. It is noted that this preamble serves no useful purpose other than synchronization; it is a penalty or overhead to the communication system and must be sent every time a burst of data is transmitted. Therefore, it is desirable to minimize the length of this preamble.
The most widely used means of acquiring the proper sample clock from the incoming data signal is an analog phase-locked loop (PLL). The phase-locked loop, such as that disclosed in "A CMOS Ethernet Serial Interface Chip" by Haung et al., 1984 ISSCC Digest, 13.1 pp. 184, 185, locks onto the transitions in the incoming preamble and maintains that condition throughout the reception of the data. However, because of the loop-filter portion of the PLL, the PLL takes many (e.g. 20 to 30) transitions of the signal in the preamble to acquire lock. Further, the phase of the clock signal from the PLL is not necessarily suitable for the sample clock. Due to the inherent nature of analog PLLs, there will be a phase difference between the incoming signal and the derived clock. Hence, additional circuitry is necessary to adjust the phase of the clock from the PLL to get the proper sample clock. Therefore, it is desirable to derive the proper sample clock from incoming burst data signal with a minimum number of transitions in the preamble, thereby allowing for a reduction in the length the preamble, and use a minimum of extra hardware.